IC 74245 DATASHEET PDF

IC 74245 DATASHEET PDF

Rev. 4 — 26 February Product data sheet. Table 1. Ordering information. Type number. Package. Temperature range Name. Description. Version. 74LS, 74LS Datasheet, 74LS Octal Bus Transceiver Tri-State Datasheet, buy 74LS, 74LS pdf, ic 74LS Lead Small Outline Integrated Circuit (SOIC), JEDEC MS, Wide. DM74LSSJ. M20D. Lead Small Outline Package (SOP), EIAJ TYPE II.

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IC integrated circuit integrierter Schaltkreis.

ABQ Techzonics TTL 54xxx, 74xxx SERIES DIGITAL ICs

Aus ibKastl GmbH Wiki. Ansichten Lesen Quelltext anzeigen Versionsgeschichte. Diese Seite wurde zuletzt am 7. Mai um Quiescent power supply current; the current flowing into the V CC supply terminal.

Additional quiescent supply current per input pin at a specified input voltage and V CC. Quiescent power supply current; the current flowing into the GND terminal. Input leakage current; the current flowing into a device at a specified input voltage and V CC.

Input diode current; the current flowing into a device at a specified input voltage. Output source or sink current; the current flowing into a device at a specified output voltage.

Output diode current; the current flowing into a device at a specified output voltage. Analog switch leakage current; the current flowing into an analog switch at a specified voltage across the switch and V CC. Supply voltage; for a device with a single negative power supply, the most negative power supply, used as the reference level for other voltages; typically ground.

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Hysteresis voltage; difference between the trigger levels, when applying a positive and a negative-going input signal. LOW level input voltage; the range of input voltages that represents a logic LOW level in the system.

HIGH level output voltage; the range of voltages at an output terminal with a specified output loading and supply voltage. Device inputs are conditioned to establish a HIGH level at the output.

Datasheet(PDF) – Fairchild Semiconductor

LOW level output voltage; the range of voltages at an output terminal with a specified output loading and supply voltage. Device inputs are conditioned to establish a LOW level at the output. ON-resistance; the effective ON-state resistance of an analog switch, at a specified voltage across the switch and output load. D ON-resistance; the difference in ON-resistance between any two switches of an analog device at a specified voltage across the switch and output load.

7400 series library in VHDL

Input capacitance; the capacitance measured at a terminal connected to an input of a device. Output load capacitance; the capacitance connected to an output terminal including jig and probe dahasheet.

Power dissipation capacitance; the capacitance used to determine the dynamic power dissipation per logic function, when no extra load is provided to the device. Switch capacitance; the capacitance of a terminal to a switch of an analog device. Input frequency; for combinatorial logic devices the maximum number of inputs and outputs switching in accordance with the device function table.

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For sequential logic devices the clock frequency using alternate HIGH and LOW for data input or using the toggle mode, whichever is applicable. Hold time; he interval immediately following the active transition of the datashset pulse usually the clock pulse or following the transition of the control input to its latching level, during which interval the data to be recognized must be maintained at the input to ensure their continued recognition.

Multiplexing a 7107 DVM IC

A negative hold time indicates that the correct logic level may be released prior to the timing pulse and still be recognized. Set-up time; the interval immediately preceding the active transition of the timing pulse usually the clock pulse or preceding the transition of the control input to its latching level, during which interval the data to be recognized must be maintained at the input to ensure their recognition.

A negative set-up time indicates that the correct logic level may be initiated sometime after the active transition of the timing pulse and still be recognized.